=== 招聘信息 ===
公司名称:北京铿腾cadence电子科技有限公司
招聘职位(一):Sr.AMS Simulator Verfication
Technique Stuff[急聘]
截至日期:2006-3-16
最低学历:硕士
招聘人数:[1]人
工作地点: 北京
简历投递与岗位查询处:
http://www.jobmm.com/cadence/Kuntai_job.asp
岗位描述:
Job Responsibilities
- Involved in the verification and validation of
the analog and analog mixed signal simulators.
- Participate in the discussions with R&D team as
the quality advocate to improve the quality of
Simulation's products.
- Write and execute test specifications and test
plans.
相关要求:
Job Requirements
- Must be a fast learner, and have a strong drive
to find bugs in software products.
- Must be independent and must be able to work on
multiple projects at a time.
- Must have RF design experience or knowledge.
- Must have Analog/Digital/Mixed Signal design
experiences.
- Coding experience with C/C++ under Linux or UNIX
preferred.
- Matlab experience preferred.
- Strong knowledge of spice/spectre netlist
preferred.
- Knowledge of verilog/ahdl simulator preferred.
- Experience on product quality testing a plus.
GUI based testing experience a plus.
- Bachelor CS/EE + 2 years or MS + 1 year
experience in EDA and/or SQA industry.
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招聘职位(二):Sr.Technique Stuff for Verilog
-A Simulator Devlp.[急聘]
截至日期:2006-3-16
最低学历:硕士
招聘人数:[1]人
工作地点: 北京
简历投递与岗位查询处:
http://www.jobmm.com/cadence/Kuntai_job.asp
岗位描述:
Job Responsibilities
- Develop, enhance and maintain Verilog-A simulator.
相关要求:
Job Requirements
- Familiar with Spice, Verilog-A, Verilog-AMS language.
- Skilled in C++ programming, familiar with development
under Linux/Unix environment.
- Analog circuit or digital simulator development
experiences. Well understanding on circuit simulation
technology, including MNA, dc, tran method.
- Good mathmatic background & knowledge.
- Be familiar with Analog design is a plus.
- EE or CS Master degree with at least 2 years related
working experience or above.
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招聘职位(三):Member of Technique Stuff for
AMS Simulator Develo[急聘]
截至日期:2006-3-9
最低学历:硕士
招聘人数:[1]人
工作地点: 北京
简历投递与岗位查询处:
http://www.jobmm.com/cadence/Kuntai_job.asp
岗位描述:
Job Responsibilities
- Develop, enhance and maintain mixed signal
circuit simulator which support Verilog-A,
Verilog-AMS, VHDL-AMS in spice netlist,
with some direction from manager or senior
engineers.
相关要求:
Job Requirements
- Familiar with Spice, Verilog, Verilog-A,
Verilog-AMS, VHDL-AMS language.
- Analog circuit or digital simulator development
experiences.
- Skilled in C++ programming, familiar with
development under Linux/Unix environment.
- Be familiar with Analog Mixed-signal design
is a plus.
- EE or C
